I2S has recently become a topic of discussion, I thought I would try and clear the water with regards, Antipodes and I2S
Antipodes Audio currently has I2S via HDMI and RJ45 on the OLADRA, K50 (original K50 HDMI only) and the K22.
The S20 via HDMI only.
The HDMI runs on LVDS and has dip switches on the underside of the units to set for DSD playback, the dip switches are only required for DSD playback, and only for the HDMI output.
Antipodes Audio devices with dip switches are set at PSAudio standard at factory.
The RJ45 runs on LVCMOS, and connects to a great number of DACs without issue, however, there are a number of manufacturers that have assigned different pin connections so a custom cable may be required.
I will try to add to this thread when more data becomes available and will lock it, if you need to enquire regarding your DAC, please post a seperate topic or PM me.
1 Like
Antipodes Pin Config
I2S over HDMI socket, supplying four signals MCLK, BCLK, LRCLK, SDATA each over an
LVDS differential pair feeding 100ohms. The DSD_ON which asserts true for DoP, and can be
configured to pin 13,14, 15 or 16. Provides PCM at 44.1, 48, 88.2, 96, 176.4, 192, 352.8, 384KHz
and DSD64 (2.8MHz), DSD128 (5.6MHz), DSD256 (11.2MHz) DoP native. The phase of each of
the DSD-LR, BCLK, LRCLK and SDATA pairs can be defined by switch setting as described
below.
This should be the pin config for connection of the Antipodes to the Ayon
Note that the RJ45 cable will have an Ayon end and an Antipodes end (Std RJ45)and needs to be installed the right way round.
For connection via AQ Link, see pin to pin spec.
Note that the RJ45 cable will have an Aqua end and an Antipodes end (Std RJ45)and needs to be installed the right way round.
Antipodes Config
I2S over HDMI socket, supplying four signals MCLK, BCLK, LRCLK, SDATA each over an
LVDS differential pair feeding 100ohms. The DSD_ON which asserts true for DoP, and can be
configured to pin 13,14, 15 or 16. Provides PCM at 44.1, 48, 88.2, 96, 176.4, 192, 352.8, 384KHz
and DSD64 (2.8MHz), DSD128 (5.6MHz), DSD256 (11.2MHz) DoP native. The phase of each of
the DSD-LR, BCLK, LRCLK and SDATA pairs can be defined by switch setting as described
below.
HDMI pinout
1 Data+
2 Gnd
3 Data4 BCLK+
5 Gnd
6 BCLK7 LRCLK+
8 Gnd
9 LRCLK10 MCLK+
11 Gnd
12 MCLK13 DSD-ON1
14 DSD-ON2
15 DSD-ON3
16 DSD-ON4
17 Gnd
18
19
